A first-in first-out buffer (FIFO) is a specialized memory circuit that is read from with one port and written to with another port. All of the data in the FIFO memory is read out in the exact same order that it was written into the FIFO memory. A FIFO memory reads only sequentially from a random access memory, where the read pointer loops back to the beginning of the RAM when it reaches the end of the RAM. The FIFO memory also writes sequentially to the RAM, where the write pointer similarly loops back to the beginning of the RAM when it reaches the end of the RAM. A FIFO memory is typically able to detect both when it is filled and when it is empty. Further, a typical FIFO memory allows simultaneous read and write operations. FIFO memories can optionally be designed to allow read and write operations from and to different clock domains.
FIFO memory implementation is typically accomplished with what is designated as a 211 memory that is organized as a ring buffer, where the numbers 211 refer to 2 total ports, 1 port configured for reading from the RAM, and 1 port configured for writing to the RAM, respectively. Other FIFO memory designs use 222 memories. FIFO memory is typically implemented using a single block of 211 or 222 memory, where the memory block is always enabled.
Current FIFO memory designs tend to require a relatively large amount of surface area in an integrated circuit, because of the relatively low density of both 211 and 222 memories. A 111 memory (one port, configured to both read and write) has a higher bit density than 211 or 222 memories, meaning that a 111 design can hold a larger memory in a given amount of space within the integrated circuit than either a 211 or a 222 design. A 211 memory generally requires about fifty percent more area than a 111 memory, and a 222 memory requires roughly one hundred percent more area than a 111 memory. However, 211 and 222 memories each have an additional port that a 111 memory does not have, which enables a single block of the 211 and 222 memories to be simultaneously written to and read from, where a 111 cannot receive such simultaneous access. Thus, 111 memory has not been used for FIFO memory designs.
In addition, FIFO memory designs tend to require a relatively large amount of power, due to the power requirements of the different memory blocks used within the FIFO memory.
What is needed, therefore, is a system that overcomes problems such as those described above, at least in part.